1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same.
2. Description of the Related Art
In a prior art, a vertical transistor has been proposed, as disclosed in US2004-262681 A1. The vertical transistor is a kind of transistor where source and drain regions are formed at upper and lower regions of a pillar region which protrudes upwards from a semiconductor substrate. When turning on the vertical transistor, a channel region is formed in a direction perpendicular to a main surface of the semiconductor substrate.
Meanwhile, it recently requires that consumption current, in particular, standby current of the semiconductor device should reduce. Most of such standby current result from GIDL (Gate Induced Drain Leakage) of the transistor included in the semiconductor device. In the following, how GIDL occurs will be explained referring to, for example, N type channel transistor. When the transistor remains idle, a gate electrical potential is kept with a lower level than a drain electrical potential. At this time, an overlapping portion between a gate electrode and a drain region comes into a deep depression state and, thus, electron-hole pairs are generated. The electrons within the pairs drift into the drain region to generate GIDL. Meantime, the holes within the pairs diffuse into the substrate to generate a substrate electrical current.
In the vertical transistor, the channel region is formed in a direction perpendicular to a main surface of the semiconductor substrate. Moreover, there exists the overlapping portion. These characteristics of the vertical transistor are the same as those of a conventional planar transistor. For this reason, in the vertical transistor, GIDL also occurs in the same manner as explained above.
In order to suppress GIDL from occurring, a structure in which the overlapping portion is diminished or eliminated has been employed. For example, FIG. 1A shows the structure in which the overlapping portion is diminished. Further, FIG. 1B shows the structure in which the overlapping portion is eliminated. Those structures are disclosed in JP2004-158585.